The present invention relates to automatic test equipment for testing integrated electronic circuits, and more particularly to such systems using a processor per pin architecture.
As the complexity and pin count of VLSI integrated circuits have exploded, test program generation has become immensely more complicated. VLSI semiconductor manufacturers are using the data from the simulation of these complex IC's to generate timing information and test vectors for the test program. In most cases either the input data to, or output data from the simulator must be modified, before timing and test vectors can be generated with this simulation data. This is primarily due to the difference in the technique in which the simulator and test systems handle waveform generation.
Timing/logic simulators work with transitions in the input and output waveforms to the IC which are called events (i.e., event driven simulation). Test systems generate waveforms by trying to fit a certain format around these transitions and then programming the time at which these transitions are to occur with edges from a timing generator. The IC simulation is not restricted to using formats or limiting the number of transitions that occur in a period of time. Often a simulation will contain waveforms that the test system can not produce. One solution is to perform a special simulation in which the input data to the simulator has been modified so that the simulation will not contain waveforms that cannot be produced on the test system. Another approach is to modify the simulation output t make the data fit the test system. Modifying the input or output of the simulation has several negative effects:
Increases test program generation time. PA1 Reduces the accuracy of the test by diverging from the intent of the simulation. PA1 Increases debug time if modifications to the simulation output create errors. PA1 Establish the device inputs. PA1 Wait for the device to respond. PA1 Check the device outputs. PA1 Drive to HIGH PA1 Drive to LOW PA1 Drive OFF PA1 Begin Test for HIGH PA1 Begin Test for LOW PA1 Begin Test for Z-State PA1 End Test
When digital functional automatic test equipment first became popular in the latter part of the 60's, its architecture was very straightforward. Latches written by controllers formed the stimulus for the device under test, and comparators on the outputs would verify the device response. Each succeeding digital functional test consists of the following sequence of events:
For each device pin, at any given instant in time at most one of the following state changes can occur:
Complexity arises because different pins require different sequences of events, and the timing at which the state changes are to occur will in general vary from pin to pin.
Test system architectures in the sixties and seventies evolved to minimize the hardware required to effectively produce large sequences of pin events. The principal architectural innovation of that period was the separation of functional data from timing, resulting in the development of very deep pattern memory applied with shared timing generators (TG's). The functional data appeared as tables of 1's and 0's (test vectors). Very effective functional tests could be produced for complex devices with just a few timing generators connected to pattern data by multiplexers and formatters. But this architectural construction, effective as it was at that time, introduced difficulties of its own. As devices become more complex, the process of parsing the test requirement into the pattern table and the timing became increasingly difficult. Limited numbers of timing resources inevitably imposed increasingly stringent restrictions on their use. The translation from the simulator output to the test program became increasingly more obscure and problematical. At the same time, device speeds dramatically increased, which made test margins ever more difficult to obtain. Pin skew and timing generator distribution skew began to dominate tester performance considerations.
During the last decade, TG-per-pin test systems were introduced to help alleviate some of these problems. As more and more resources are applied independently to each of the device pins, fewer and fewer machine restrictions are imposed on the functional test program. But simply applying a TG per pin does not eliminate the translation problem. The need to modify the simulation data exists regardless of whether the test system has shared resource timing or TG-per-pin timing architecture. The TG-per-pin architecture allows the flexibility to generate independent waveforms on every device pin, but still restricts the waveforms with tester oriented formats and limited transitions. Furthermore, many of the available TG-per-pin systems do not provide calibrated edge placement on all functions. Thus manual changes to the timing are still required to get adequate yields.